The typical arrangement for use of synchronous microprocessors is to run both microprocessors asynchronously and compare the results of their operations at the end of each task. The faster microprocessor is then allowed to wait for a period of time while the slower microprocessor presents its results to a comparison circuit. Thus, the microprocessors are not actually run in synchronism, but rather, the microprocessors are continuously resynchronized after a predetermined number of operations.
The present invention enables two microprocessors to actually be run synchronously with their address, date and status bits being compared during each bus cycle.